职责范围：1. Physical implementation of advanced technology chips.2. Design methodology development and innovation for advanced technology challenges.3. Be responsible for 22/16/12/10/7/5nm chip implementation for customer’s projects or internal system test chips.4. Be responsible for advanced node PPA benchmark, and solution development.5. EDA tool new features enablement. 6. Customer onsite/offsite supports will be required on demand. 负责先进芯片技术的物理实现。负责先进技术之设计方法的开发与创新。负责16 / 10 / 7/5纳米之客户项目或内部系统测试芯片的实施。负责完善EDA工具及客户支持。职位要求： 1. MS or above in EE, CS related fields. Experience in APR, physical verification, chip implementation, or CAD development is plus.2. 3 years working experience in chip physical implementation.3. Familiar with Synopsys/Cadence APR tools/flows.4. Familiar with TCL/Perl/Python programming.5. Experience with TSMC advanced technology is plus.6. Proven record in production tape-outs is plus.微电子、计算机科学、电子科学与技术等相关领域知识的硕士含以上人员。具有APR、物理验证、芯片的实现经验及CAD开发经验者优先。熟悉Synopsys/Cadence APR 工具及流程。熟悉 tcl/perl 程序。具有TSMC先进技术经验的人员优先。具有成功流片经验优先。 职能类别：集成电路IC设计/应用工程师